Integrated Nanowire Systems for Post-CMOS Computing

CMOS faces new device and technology challenges: MOSFETs require ultra-sharp doping profiles and complex processing; integration of devices into circuits requires arbitrary interconnection with overlay precision beyond known manufacturing solutions (3σ=±3nm, 16nm CMOS, ITRS’11[1]). To overcome these challenges, we propose a new nanoscale computing fabric with integrated design of device, interconnect and circuits to minimize manufacturing requirements while providing ultra-dense, high-performance, and low-power solution surpassing scaled CMOS. Devices with uniform doping profiles, regular arrays tolerant to mask misalignment and novel circuits with limited customization are discussed. Device evaluations prove that proposed devices simplify manufacturing complexity vs. CMOS while being competitive (ION = 14μA, ION/IOFF > 10 6 ). Simulations show 100% yield at overlay imprecision as high as 3σ=±8nm (manufacturing solutions known, ITRS’11[1]). Benchmarking of processor design vs. equivalent 16nm CMOS shows 3x density, 5x power benefits at comparable performance. Memory benchmarking shows 35x leakage power, 3x performance improvement over 16nm SRAM.